1. Field of the Invention
This invention relates to electronic circuits that generate a constant reference voltage that is independent of a power supply voltage source. More particularly, this invention relates to start-up circuits connected to reference voltage generation circuits that will force the reference voltage generation circuits to the constant reference voltage at the initiation of the power supply voltage source.
2. Field of the Related Art
FIG. 1 illustrates a reference voltage generation circuit that is independent of the voltage level of the power supply voltage source. The reference voltage generation circuits have a pair of P-type Metal Oxide Semiconductor (MOS) Field Effect Transistors (FET) P1 and P2. The gates of the PMOS FET's P1 and P2 have their gates commonly connected together and to the drain of the second PMOS FET P2. The sources of the PMOS FET's P1 and P2 are connected to the positive terminal of the power supply voltage source. The reference voltage generation circuit, further, has two N-type MOS FET's N1 and N2. The NMOS FET's N1 and N2 have their gates commonly connected together and to the drains of the first PMOS FET P1 and the first NMOS FET N1 to form the reference output terminal REF. The reference output terminal contains the supply independent reference voltage. The source of the first NMOS FET N1 is connected to the ground reference terminal of the power supply voltage source. The drain of the second NMOS FET N2 is connected to the drain of the second PMOS FET P2 and the commonly connected gates of the PMOS FET's P1 and P2.
A resistor R0 is connected between the source of the second NMOS FET N2 and the ground reference terminal of the power supply voltage source.
The reference voltage generation circuit has two operational modes. In the normal operational mode, the reference voltage level at the output reference terminal REF is determined by the device parameters of the second PMOS FET P2 and the second NMOS FET N2 and the resistance value of the resister R0. The second mode occurs during initiation of the power supply voltage source. At this time all the MOS FET's have zero current flowing in them and zero voltage developing across them. This second mode prohibits the voltage level at the output reference terminal REF from achieving the reference voltage level without assistance.
U.S. Pat. No. 5,243,231 (Baik) provides a start-up circuit for the reference voltage generation circuit as shown in FIG. 2. The start-up circuit is composed of the resistor R2 and the capacitor C1. Current flows through the resistor R2 and the capacitor C1 during the initiation of the power supply voltage source. This places a voltage at the output reference terminal REF sufficient to turn on the first NMOS FET N1 to begin to sink current. The first PMOS FET P1 is then turned on as a result of the current in the first NMOS FET N1. As a result of the first PMOS FET P1 turn-on, the second PMOS FET P2 and the second NMOS FET N2 turn-on, the reference voltage generation circuit assumes the first operational mode having the reference voltage level present at the output reference terminal REF.
A problem with the start-up circuit of Baik is that any variations or noise present on the power supply voltage source is coupled through the resistor R2 and capacitor C1 to the output reference terminal REF. This causes undesired variations in the reference voltage level.
FIG. 3 shows a start-up circuit of the prior art as shown in U.S. Pat. No. 5,565,811 (Park et al.). The start-up circuit has a serial string of multiple diode connected PMOS FETs, PP0, PP1, PP2, . . . , PPn. The serial string of diode connected PMOS FET PPO, PPI, PP2, . . . , PPn each have their drains connected to the gate and to the source of the subsequent diode connected PMOS FET. The source of the first diode connected PMOS FET PPO is connected to the positive terminal of the power supply voltage source. The commonly connected drain and gate of the last diode connected PMOS FET PPn is connected to the ground reference terminal of the power supply voltage source.
A third PMOS FET P23 has its source connected to the commonly connected gates of the first and second PMOS FET's P1 and P2, its drain connected to the ground reference terminal of the power supply voltage source, and its gate connected to the junction B of the second and third of the serial diode connected PMOS FET's PP1 and PP2.
At the initiation of the power supply voltage source, the voltage level present at the junction B is the voltage level of the power supply voltage source less twice the threshold voltage level (V.sub.cc -2V.sub.TH). This voltage is sufficient to cause the third PMOS FET P23 to begin to conduct causing the second PMOS FET P2 to turn on and consequently causing the first PMOS FET P1 and the first and second NMOS FET's N1 and N2 to turn on establishing the reference voltage level at the output reference terminal REF. The start-up circuit of FIG. 3 has a current flowing constantly when the power supply voltage source it turned on. This is a waste of power and requires a static current to be provided by the power supply voltage source.
To eliminate the static current of the start-up current of FIG. 3 Park et al. describe a start-up circuit as shown in FIGS. 4 and 5. In this case the start-up circuit is composed of a serial string of diode connected NMOS FET's NN1, NN2, . . . , NNn. The diode connected NMOS FET have the gate connected to the drain of each NMOS FET as described above. A third NMOS FET N3 has its gate connected to a start-up terminal that will provide a start-up enable signal during the initiation of the power supply voltage source. The drain of the third MOS FET N3 is connected to the commonly connected gates of the first and second PMOS FET's P1 and P2 as shown in FIG. 5 or to the positive terminal of the power supply voltage source of FIG. 4. The source of the third NMOS FET N3 is connected to the commonly connected gate and drain of the first diode connected NMOS FET NN1.
The source of the last diode connected NMOS FET NNn is connected to the ground reference terminal of the power supply voltage source as shown in FIG. 5 or the output reference terminal REF in FIG. 4.
In FIG. 4, the start-up enable signal turns on the third NMOS FET N3. The current through the serial string of diode connected NMOS FET's NN1, NN2, . . . , NNn increases the voltage level at the output reference terminal sufficient to turn on the first NMOS FET N1. As described above, the current in the first NMOS FET N1 causes the second NMOS FET N2 and the first and second PMOS FET's P1 and P2 to activate to establish the reference voltage level at the output reference terminal.
In the start-up circuit of FIG. 5, the start-up enable signal turns on the third NMOS FET N3 causing current to flow in the serial string of diode connected NMOS FET's NN1, NN2, . . . , NNn. This causes the second PMOS FET P2 to turn on and consequently the first PMOS FET P1 and the first and second NMOS FET's N1 and N2. This establishes the reference voltage level at the output reference terminal REF as described above.
In both examples, the start-up enable signal will assume a disable state when the voltage level of the power supply voltage source attains its final level. The third NMOS FET N3 becomes turned off and no current is flowing in the start-up circuit.
FIG. 6 illustrates an example of the start-up circuit of Park et al. The PMOS FET P62 and the NMOS FET N60, the PMOS FET P63 and NMOS FET N61, the PMOS FET P64 and the NMOS FET N63 are each configured as a CMOS inverter. The PMOS FET P60 has its source connected to the positive terminal of the power supply voltage source, its gate connected to the ground reference terminal of the power supply voltage source and its drain connected to the diode connected PMOS FET P61. The gate and drain of the diode connected PMOS FET P61 is connected to the commonly connected gates of the PMOS FET P62 and the NMOS FET N60. The capacitor C60 is connected between the gate and drain of the diode connected PMOS FET P61 and the ground reference terminal of the power supply voltage source.
The drains of the PMOS FET P62 and the NMOS FET N60 are connected to the commonly connected gates of the PMOS FET P63 and the NMOS FET N61. The capacitor C61 is connected between the commonly connected gates of the PMOS FET P63 and NMOS FET N61 and the positive terminal of the power supply voltage source.
The drains of the PMOS FET P63 and NMOS FET N61 are connected to the commonly connected gates of the PMOS FET P64 and the NMOS FET N63. The capacitor C62 is connected between the commonly connected gates of the PMOS FET P64 and the NMOS FET N63 and the ground reference terminal of the power supply voltage source. The drains of the PMOS FET P64 and the NMOS FET N63 are connected to the start-up enable terminal SU to transfer the start-up enable signal to the start-up circuits of FIG. 4 and 5.
It can be seen that upon initialization of the power supply voltage source, i15 the start-up enable signal is close to the voltage level of the power supply voltage source thus turning on the third NMOS FET transistor N3 of the FIG. 4 and 5. When the capacitors C60, C61 and C62 has been charged to their correct values, the voltage level at the start-up enable terminal SU is sufficient to turn off the third NMOS FET transistor N3 of FIG. 4 and FIG. 5 thus disabling the start-up circuits. The start-up circuit of FIG. 4 and 5 and the start-up enable circuit of FIG. 6 require additional circuitry and add complexity to the reference voltage generation circuits of the prior art.
U.S. Pat. No. 5,825,237 (Ogawa) describes a reference voltage generation circuit similar to that of Park et al. The reference voltage generation circuit has a reference voltage circuit and a power source start circuit for starting the reference voltage circuit at the time of closure of the power source. This is to prevent fluctuations in the reference voltage during sharp fluctuations in the voltage level of the power source.
U.S. Pat. No. 5,155,384 (Ruetz) describes a start-up circuit for a bias or reference voltage generating circuit. The start-up circuit of Ruetz provides current source for providing a small charging current and transistors for coupling the charging current to the bias generating circuit during initiation of a power supply voltage source to force the bias generating circuit to the normal operational state. The start-up circuit uncouples the current source from the bias generating circuit after it has the normal operational state to prevent the charging current from affecting the operation of the bias generating circuit.
U.S. Pat. No. 5,867,013 (Yu) illustrates a start-up circuit for a band-gap reference voltage circuit. When the output of the band-gap reference circuit is below a start-up voltage threshold the start-up circuit provides a voltage at the input of the band-gap reference circuit sufficient to cause the band-gap reference circuit to produce the desired output voltage.
Once the output of the band-gap has reached the start-up threshold voltage the start-up circuit is disabled and does not interfere with the normal operation of the band-gap reference circuit.